Probabilistic Retiming: A Circuit Optimization Technique

VLSI circuit manufacturing may result in devices with di erent propagation delays. Hence, the estimation of such delays during the design procedure may not prove totally accurate due to the fabrication process. This paper presents a new optimization methodology, called probabilistic retiming, which transforms a circuit based on statistical data gathered from the production history. Such circuits are modeled as graphs where each vertex represents a combinational element that has a probabilistic timing characteristic. A polynomial-time algorithm, applicable to such a graph, is developed which retimes a circuit in order to produce a design operating on a speci ed cycle time c within a given con dence level . In other words, the clock cycle of the retimed circuit is guaranteed to be less than or equal to c with at least probability . Experiments show the e ectiveness of the algorithm, subject to the designer requirements and to the manufacturing information, which is able to signi cantly improve the con dence in the fabrication yielding factors.